31 ~ 40

31 - Always if

module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
    
    assign out_assign = (sel_b1 & sel_b2) ? b : a;
    
    always @(*) begin
        if (sel_b1 & sel_b2 == 1) begin
            out_always = b;
        end
        else begin
            out_always = a;
        end
    end

endmodule

32 - Always if2

module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
            shut_off_computer = 1;
        else shut_off_computer = 0;
    end

    always @(*) begin
        if (arrived | gas_tank_empty)
           keep_driving = 0;
        else keep_driving = 1;
    end

endmodule

33 - Always case

module top_module ( 
    input [2:0] sel, 
    input [3:0] data0,
    input [3:0] data1,
    input [3:0] data2,
    input [3:0] data3,
    input [3:0] data4,
    input [3:0] data5,
    output reg [3:0] out   );//

    always@(*) begin  // This is a combinational circuit
        case(sel)
            4'd0: out = data0;
            4'd1: out = data1;
            4'd2: out = data2;
            4'd3: out = data3;
            4'd4: out = data4;
            4'd5: out = data5;
            default: out = 0;
        endcase
    end

endmodule

34 - Always case2

module top_module (
    input [3:0] in,
    output reg [1:0] pos  );
    
    always @(*) begin
        case (in)
            4'h0: pos = 2'b00;
            4'h1: pos = 2'b00;
            4'h2: pos = 2'b01;
            4'h3: pos = 2'b00;
            4'h4: pos = 2'b10;
            4'h5: pos = 2'b00;
            4'h6: pos = 2'b01;
            4'h7: pos = 2'b00;
            4'h8: pos = 2'b11;
            4'h9: pos = 2'b00;
            4'ha: pos = 2'b01;
            4'hb: pos = 2'b00;
            4'hc: pos = 2'b10;
            4'hd: pos = 2'b00;
            4'he: pos = 2'b01;
            4'hf: pos = 2'b00;
            default: pos = 2'b00;
        endcase
    end           

endmodule

35 - Always casez

module top_module (
    input [7:0] in,
    output reg [2:0] pos );
    
    always @(*) begin
        casez (in)
            8'bzzzzzzz1: pos = 8'd0;
            8'bzzzzzz1z: pos = 8'd1;
            8'bzzzzz1zz: pos = 8'd2;
            8'bzzzz1zzz: pos = 8'd3;
            8'bzzz1zzzz: pos = 8'd4;
            8'bzz1zzzzz: pos = 8'd5;
            8'bz1zzzzzz: pos = 8'd6;
            8'b1zzzzzzz: pos = 8'd7;
            default: pos = 8'd0;
        endcase
    end
    
endmodule