01 ~ 10

01 - Step one

module top_module( output one );

// Insert your code here
    assign one = 1;

endmodule

02 - Zero

module top_module(
    output zero
);// Module body starts after semicolon
    assign zero = 0;

endmodule

03 - Wire

module top_module( input in, output out );
    assign out = in;

endmodule

04 - Wire4

module top_module( 
    input a,b,c,
    output w,x,y,z );
    
    assign w = a;
    assign x = b;
    assign y = b;
    assign z = c;

endmodule

05 - Notgate

module top_module( input in, output out );
    assign out = ~in;

endmodule

06 - Andgate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = a&b;

endmodule

07 - Norgate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = ~(a|b);

endmodule

08 - Xnorgate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = ~(a^b);

endmodule

09 - Wire decl

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    assign out = (a&b) | (c&d);
    assign out_n = ~out;

endmodule

10 - 7458

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    assign p2y = (p2a & p2b) | (p2c & p2d);
    assign p1y = (p1a & p1c & p1b) | (p1f & p1e & p1d);


endmodule