목록FPGA(중단) (20)

Hueestory

31 ~ 40

31 - Always if module top_module( input a, input b, input sel_b1, input sel_b2, output wire out_assign, output reg out_always ); assign out_assign = (sel_b1 & sel_b2) ? b : a; always @(*) begin if (sel_b1 & sel_b2 == 1) begin out_always = b; end else begin out_always = a; end end endmodule 32 - Always if2 module top_module ( input cpu_overheated, output reg shut_off_computer, input arrived, inpu..
FPGA(중단)/HDLbits 2023. 3. 29. 17:34
09 LED toggle

Vivado를 사용해 Zynq IP 생성 → Vitis를 사용해 C 코딩 1. LED on / 'LED is ON' 출력 2. sleep 1s 3. LED off / 'LED is OFF' 출력 4. sleep 1s * while을 통해 무한루프 * sleep 함수는 vitis에서 이용할 수 없으므로 sleep.h의 usleep 사용 (usleep은 micro second 단위를 사용하므로 usleep(1000000) → 1초 대기) Vitis C Code #include #include "sleep.h" #include "xgpiops.h" #include "platform.h" int main() { static XGpioPs psGpioInstancePtr; XGpioPs_Config * GpioC..
FPGA(중단)/zynq 2023. 3. 22. 14:36
08 PL with AXI

Vitis C Code #include #include "xgpio.h" #include "xgpiops.h" #include "platform.h" int main() { static XGpio GPIOInstance_Ptr; static XGpioPs psGpioInstancePtr; XGpioPs_Config *GpioConfigPtr; u8 count = 0; int xStatus; int BtnPinDirection1 = 0, BtnPinNumber1 = 50; int Readstatus = 0, OldReadstatus = 0; init_platform(); // Step 01 : AXI GPIO Initialization // xStatus = XGpio_Initialize(&GPIOInst..
FPGA(중단)/zynq 2023. 3. 14. 14:39
AMBA Bus Summary(txt)

- 여러 Block들이 상호 Data를 전송하기 위해 이들을 전기적으로 연결한 공유 신호선 장점- 인터페이스의 간소화 : IP Block들을 wire로 point-to-point 방식으로 잇게 되면 선이 많고 복잡함 - 확장성 : IP Block을 추가할 때 Bus에만 연결하면 됨 - APB, AHP, AXI : Performance를 위해 Bus 분리 - 빠른 동작이 필요 없는 것들은 APB와 같은 저속 Bus에 연결 - 빠른 동작이 필요한 것들은 AHB와 같은 고속 Bus에 연결 - 전력 소비를 최소화하고 인터페이스의 복잡성을 줄이기 위해 최적화된 저가형 인터페이스 - 고성능을 요구하지 않는 주변 장치를 위한 Bus - 인터페이스의 간소화, 확장성- APB Process1. Master는 여러 S..
FPGA(중단)/verilog 2023. 3. 9. 21:14
07 PS MIO

Vitis C Code #include #include "xgpiops.h" #include "platform.h" int main() { static XGpioPs psGpioInstancePtr; XGpioPs_Config * GpioConfigPtr; int xStatus; int BtnPinDirection = 0, BtnPinNumber = 50; int LedPinDirection = 1, LedPinNumber = 7; int Readstatus = 0, OldReadstatus = 0; init_platform(); print("Hello World\n\r"); // step 1 : PS GPIO Initialization // GpioConfigPtr = XGpioPs_LookupConf..
FPGA(중단)/zynq 2023. 3. 3. 20:49
AXI block design

FPGA(중단)/verilog 2023. 2. 24. 14:11
AXI protocol

AXI protocol : A point-to-point connection I used Vivado 2019.2 and referred to the https://support.xilinx.com/s/article/1058302?language=en_US site.
FPGA(중단)/verilog 2023. 2. 24. 14:08
21 ~ 30

21 - Module pos module top_module ( input a, input b, input c, input d, output out1, output out2 ); mod_a (out1, out2, a, b, c, d); endmodule 22 - Module name module top_module ( input a, input b, input c, input d, output out1, output out2 ); mod_a (.in1(a), .in2(b), .in3(c), .in4(d), .out1(out1), .out2(out2)); endmodule 23 - Module shift module top_module ( input clk, input d, output q ); wire ..
FPGA(중단)/HDLbits 2023. 2. 22. 11:05
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