21 ~ 30

21 - Module pos

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a (out1, out2, a, b, c, d);

endmodule

22 - Module name

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a (.in1(a), .in2(b), .in3(c), .in4(d), .out1(out1), .out2(out2));

endmodule

23 - Module shift

module top_module ( input clk, input d, output q );
    
    wire q1;
    wire q2;
    
    my_dff u1 (.clk(clk), .d(d), .q(q1));
    my_dff u2 (.clk(clk), .d(q1), .q(q2));
    my_dff u3 (.clk(clk), .d(q2), .q(q));

endmodule

24 - Module shift8

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    wire [7:0] q1;
    wire [7:0] q2;
    wire [7:0] q3;
    
    my_dff8 u1 (.clk(clk), .d(d), .q(q1));
    my_dff8 u2 (.clk(clk), .d(q1), .q(q2));
    my_dff8 u3 (.clk(clk), .d(q2), .q(q3));
    
    always@(*)
        if (sel == 2'b00) q = d;
    	else if (sel == 2'b01) q = q1;
    	else if (sel == 2'b10) q = q2;
    	else if (sel == 2'b11) q = q3;
    
endmodule

25 - Module add

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire [15:0] a_hi = a[31:16];
    wire [15:0] a_lo = a[15:0];
    wire [15:0] b_hi = b[31:16];
    wire [15:0] b_lo = b[15:0];

    wire cout1;
    wire cout2;
    wire [15:0] sum_hi;
    wire [15:0] sum_lo;
    
    add16 u1 (.a(a_lo), .b(b_lo), .cin(1'b0), .sum(sum_lo), .cout(cout1));
    add16 u2 (.a(a_hi), .b(b_hi), .cin(cout1), .sum(sum_hi), .cout(cout2));

    assign sum = {sum_hi, sum_lo};
    

endmodule

26 - Module fadd

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);//
    wire [15:0] a_hi = a[31:16];
    wire [15:0] a_lo = a[15:0];
    wire [15:0] b_hi = b[31:16];
    wire [15:0] b_lo = b[15:0];

    wire cout1;
    wire cout2;
    wire [15:0] sum_hi;
    wire [15:0] sum_lo;
    
    add16 u1 (.a(a_lo), .b(b_lo), .cin(1'b0), .sum(sum_lo), .cout(cout1));
    add16 u2 (.a(a_hi), .b(b_hi), .cin(cout1), .sum(sum_hi), .cout(cout2));

    assign sum = {sum_hi, sum_lo};

endmodule

module add1 ( input a, input b, input cin,   output sum, output cout );

// Full adder module here
    assign sum  = a ^ b ^ cin;
    assign cout = (a&b) | (a&cin) | (b&cin);

endmodule

27 - Module cseladd

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire [16:0] a_lower = a[15:0];
    wire [16:0] a_higher = a[31:16];
    wire [16:0] b_lower = b[15:0];
    wire [16:0] b_higher = b[31:16];
    
    wire cout1, cout2, cout3;
    
    wire [15:0] sum_lower;
    wire [15:0] sum_higher_0;
    wire [15:0] sum_higher_1;
    wire [15:0] sum_higher;
    
    add16 add16_u1(.a(a_lower), .b(b_lower), .cin(1'b0), .sum(sum_lower), .cout(cout1));
    add16 add16_u2(.a(a_higher), .b(b_higher), .cin(1'b0), .sum(sum_higher_0), .cout(cout2));
    add16 add16_u3(.a(a_higher), .b(b_higher), .cin(1'b1), .sum(sum_higher_1), .cout(cout2));
    
    assign sum_higher = (cout1 ? sum_higher_1 : sum_higher_0);
    assign sum = {sum_higher, sum_lower};

endmodule

28 - Module addsub

module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    
    wire [16:0] lower_a = a[15:0];
    wire [16:0] higher_a = a[31:16];
    wire cout1, cout2;
    wire [31:0]exor_b = (sub ? ~b : b);
    
    add16 add16_u1(.a(lower_a), .b(exor_b[15:0]), .cin(sub), .sum(sum[15:0]), .cout(cout1));
    add16 add16_u2(.a(higher_a), .b(exor_b[31:16]), .cin(cout1), .sum(sum[31:16]), .cout(cout2));        
    
endmodule

29 - Alwaysblock1

module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
    
    assign out_assign = a & b;
    always @(*) out_alwaysblock = a & b;

endmodule

30 - Alwaysblock2

module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
    
    assign out_assign = a^b;
    always @(*) out_always_comb = a^b;
    always @(posedge clk) out_always_ff = a^b;

endmodule