목록axi (4)

Hueestory

08 PL with AXI

Vitis C Code #include #include "xgpio.h" #include "xgpiops.h" #include "platform.h" int main() { static XGpio GPIOInstance_Ptr; static XGpioPs psGpioInstancePtr; XGpioPs_Config *GpioConfigPtr; u8 count = 0; int xStatus; int BtnPinDirection1 = 0, BtnPinNumber1 = 50; int Readstatus = 0, OldReadstatus = 0; init_platform(); // Step 01 : AXI GPIO Initialization // xStatus = XGpio_Initialize(&GPIOInst..
FPGA(중단)/zynq 2023. 3. 14. 14:39
AMBA Bus Summary(txt)

- 여러 Block들이 상호 Data를 전송하기 위해 이들을 전기적으로 연결한 공유 신호선 장점- 인터페이스의 간소화 : IP Block들을 wire로 point-to-point 방식으로 잇게 되면 선이 많고 복잡함 - 확장성 : IP Block을 추가할 때 Bus에만 연결하면 됨 - APB, AHP, AXI : Performance를 위해 Bus 분리 - 빠른 동작이 필요 없는 것들은 APB와 같은 저속 Bus에 연결 - 빠른 동작이 필요한 것들은 AHB와 같은 고속 Bus에 연결 - 전력 소비를 최소화하고 인터페이스의 복잡성을 줄이기 위해 최적화된 저가형 인터페이스 - 고성능을 요구하지 않는 주변 장치를 위한 Bus - 인터페이스의 간소화, 확장성- APB Process1. Master는 여러 S..
FPGA(중단)/verilog 2023. 3. 9. 21:14
AXI block design

FPGA(중단)/verilog 2023. 2. 24. 14:11
AXI protocol

AXI protocol : A point-to-point connection I used Vivado 2019.2 and referred to the https://support.xilinx.com/s/article/1058302?language=en_US site.
FPGA(중단)/verilog 2023. 2. 24. 14:08
이전 Prev 1 Next 다음