Hueestory

11 - Vector0 module top_module ( input wire [2:0] vec, output wire [2:0] outv, output wire o2, output wire o1, output wire o0 ); // Module body starts after module declaration assign outv = vec; assign o2 = vec[2]; assign o1 = vec[1]; assign o0 = vec[0]; endmodule 12 - Vector1 `default_nettype none // Disable implicit nets. Reduces some types of bugs. module top_module( input wire [15:0] in, out..

01 - Step one module top_module( output one ); // Insert your code here assign one = 1; endmodule 02 - Zero module top_module( output zero );// Module body starts after semicolon assign zero = 0; endmodule 03 - Wire module top_module( input in, output out ); assign out = in; endmodule 04 - Wire4 module top_module( input a,b,c, output w,x,y,z ); assign w = a; assign x = b; assign y = b; assign z ..